Datasheet4U Logo Datasheet4U.com

82093AA - I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER

Datasheet Summary

Description

at any time, without notice.

The 82093AA IOAPIC may contain design defects or errors known as errata.

Current characterized errata are available on request.

📥 Download Datasheet

Datasheet preview – 82093AA

Datasheet Details

Part number 82093AA
Manufacturer Intel Corporation
File Size 178.57 KB
Description I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER
Datasheet download datasheet 82093AA Datasheet
Additional preview pages of the 82093AA datasheet.

📁 Similar Datasheet

  • 82012 - Phase Control SCR (Powerex Power Semiconductors)
  • 8205 - LOW-DROPOUT REGULATORS (Allegro MicroSystems)
  • 8205 - N-CHANNEL POWER MOSFET (AiT Semiconductor)
  • 8205 - Dual N-Channel Power MOSFET (Fortune Semiconductor)
  • 8205A - Dual N-Channel MOSFET (RZC Microelectronics)
  • 8205A - Dual N-Channel MOSFET (HSMC)
  • 8205A - N-channel power MOSFET (ETC)
  • 8205A - Dual N-Channel MOSFET (HOTTECH)
  • 8205A - MOSFET (GOFORD)
  • 8205A - Dual N-Channel 25-V MOSFET (VBsemi)
Other Datasheets by Intel Corporation
  • 82091AA - ADVANCED INTEGRATED PERIPHERAL
  • 8203 - 64K DYNAMIC RAM CONTROLLER
  • 82077AA - CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER
  • 82078 - FLOPPY DISK CONTROLLER
  • 82078-1 - FLOPPY DISK CONTROLLER
  • 82078-3 - FLOPPY DISK CONTROLLER
  • 82078-5 - FLOPPY DISK CONTROLLER
  • 82078SL - FLOPPY DISK CONTROLLER

Full PDF Text Transcription

Click to expand full text
E PRELIMINARY 82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)  3 General Purpose Interrupts  Independently Programmable for Provides Multiprocessor Interrupt Management  Dynamic Interrupt DistributionRouting Interrupt to the Lowest Priority Processor  Software Programmable Control of Interrupt Inputs  Off Loads Interrupt Related Traffic From the Memory Bus 24 Programmable Interrupts  13 ISA Interrupts Supported  4 PCI Interrupts  1 Interrupt/SMI# Rerouting  2 Motherboard Interrupts  1 Interrupt Used for INTR Input Edge/Level Sensitivity Interrupts  Each Interrupt Can Be Programmed to Respond to Active High or Low Inputs X-Bus Interface  CS For Flexible Decode of the IOAPIC Device.
Published: |