82541ER
Overview
- PCI Bus - PCI revision 2.3, 32-bit, 33/66 MHz - Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands - 3.3 V (5 V tolerant PCI signaling) MAC Specific - Low-latency transmit and receive queues - IEEE 802.3x-compliant flow-control support with software-controllable thresholds - Caches up to 64 packet descriptors in a single burst - Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) - Wide, optimized internal data path architecture - 64 KB configurable Transmit and Receive FIFO buffers PHY Specific - Integrated for 10/100/1000 Mb/s operation - IEEE 802.3ab Auto-Negotiation support - IEEE 802.3ab PHY compliance and compatibility - State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation * * *
- - Automatic polarity detection - Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds Host Off-Loading - Transmit and receive IP, TCP, and UDP checksum off-loading capabilities - Transmit TCP segmentation - Advanced packed filtering - Jumbo frame support up to 16 KB - Intelligent Interrupt generation (multiple packets per interrupt) Manageabiltiy - Network Device Class Power Management Specification 1.1 - Compliance with PCI Power Management 1.1 and ACPI 2.0 - SNMP and RMON statistic counters - D0 and D3 power states Additional Device - Four programmable LED outputs - On-chip power control circuitry - BIOS LAN Disable pin - JTAG (IEEE 1149.1) Test Access Port built in silicon Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The
