Intel Corporation 82C55
82C55A is a high-performance CHMOS version of the industry standard 8255A general purpose programmable I O device which is designed for use with all Intel and most other microprocessors It provides 24 I O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A-5 In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and...| Part No. | 82C55 |
|---|---|
| Datasheet | 82C55 Download |
| Manufacturer |  Intel Corporation |
| Description | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| Buy | Stock & Price |
DESCRIPTION
Symbol PA3–0 RD CS Pin Number Dip PLCC 1– 4 5 6 2–5 6 7 Type I O I I Name and Function PORT A PINS 0 – 3 Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise System Ground I ADDRESS These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers A1 0 0 1 1 0 0 1 1 X X PC7–4 10– 13 11 13–15 I O A0 0 1 0 1 0 1 0 1 X X RD 0 0 0 0 1 1 1 1 X 1 WR 1 1 1 1 0 0 0 0 X 1 CS 0 0 0 0 0 0 0 0 1 0 Input Operation (Read) Port A - Data Bus Port B - Data Bus Port C - Data Bus Control Word - Data Bus Output Operation (Write) Data Bus - Port A Data Bus - Port B Data Bus - Port C Data Bus - Control Disable Function Data Bus - 3 - State Data Bus - 3 - State GND A1–0 7 8– 9 8 9–10 PORT C PINS 4 – 7 Upper nibble of an 8-bit data output latch...
