Download the A80960HT75SL2GP datasheet PDF.
This datasheet also covers the A80 variant, as both devices belong to the same 80960ha/hd/ht 32-bit high-performance superscalar processor family and are provided as variant models within a single manufacturer datasheet.
General Description
at any time, without notice.
Key Features
s
s
s s s
32-Bit Parallel Architecture.
Load/Store Architecture.
Sixteen 32-Bit Global Registers.
Sixteen 32-Bit Local Registers.
1.28 Gbyte Internal Bandwidth (80 MHz).
On-Chip Register Cache Processor Core Clock.
80960HA is 1x Bus Clock.
80960HD is 2x Bus Clock.
80960HT is 3x Bus Clock Binary Compatible with Other 80960 Processors Issue Up To 150 Million Instructions per Second High-Performance On-Chip Storage.
Full PDF Text Transcription for A80960HT75SL2GP (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
A80960HT75SL2GP. For precise diagrams, and layout, please refer to the original PDF.
80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Data Sheet Advance Information Product Features s s s s s 32-Bit Parallel Architecture —Load/Store Architectur...
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eatures s s s s s 32-Bit Parallel Architecture —Load/Store Architecture —Sixteen 32-Bit Global Registers —Sixteen 32-Bit Local Registers —1.28 Gbyte Internal Bandwidth (80 MHz) —On-Chip Register Cache Processor Core Clock —80960HA is 1x Bus Clock —80960HD is 2x Bus Clock —80960HT is 3x Bus Clock Binary Compatible with Other 80960 Processors Issue Up To 150 Million Instructions per Second High-Performance On-Chip Storage —16 Kbyte Four-Way Set-Associative Instruction Cache —8 Kbyte Four-Way Set-Associative Data Cache —2 Kbyte General Purpose RAM —Separate 128-Bit Internal Paths For Instructions/Data s s s s s 3.
A80960HT75SL2GP Datasheet
