IXF18102 Datasheet | Intel Corporation

product brief Intel IXF18102 ® 10Gbps Physical Layer Device for STS-192c/STM 64c POS/GFP .. Product Description The Intel® IXF18102 is a highly integrated framer solution for STS-192c/STM 64c port applications. The IXF18102 supports various modes of operation for transport of HDLC frames (POS) or Generic Framing Procedure (GFP) packet formatting. Internal mapping engines provide the required formatting and packet data maintenance into the STS-192c/STM 64c SONET/SDH frame payload. A data-over-Fiber packet mapping mode is supported for test equipment and test functionality verification within a system. The GFP mapping engine can be connected directly to Forward Error Correction (FEC) or OTN digital wrapper devices for GFP, per G.709 specifications. The system interface is 16 bits wide, Features 622Mbps- 800Mbps Double Data Rate (DDR) clocking and supports the industrystandard System Parallel Interface Level 4 (SPI-4) Phase 2. The SPI-4 Phase 2 interface is Low Voltage Differential Signaling (LVDS), which produces fewer connection concerns than previous 64-bit High- Speed Transport Layer (HSTL) interfaces. On the line side, the IXF18102 supports the OIF Serdes Framer Interface Level 4 (SFI-4) interface, which is 16 bits wide with 622Mbps data rate. The IXF18102 supports Automatic Protection Switching (APS) for SONET/SDH. Various types of loop backs such as line remote, line local, system remote as well as system local and Synchronous Payload Envelope (SPE) payload test are supported for general development functionality test and debug. Intel® IXF18102 Block Diagram Serial Overhead/ Alarm Interface Packet Over SONET Processor SPI-4 Phase 2 System Interface 16 16 16-bit LVDS 622Mbps 800Mbps DDR 16 16-bit LVDS 622Mbps 16 OIF SFI-4 Framer FIFO GFP Processor 16 16 APS Interface 16 Generic µP Interface 16-bit LVDS Intel® IXF1810x Family of 10Gbps Physical Layer Devices- High Level Overview Intel’s family of 10 Gigabit framer devices provide the...