Description
Symbol TEST 0 TEST 1 DIP Pin No 1 39 PLCC Pin No 2 43 QFP Pin No 18 16 Type I Name and Function TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) functions as the event timer input (under software control) TEST 0 (T0) is a multi-function pin used during PROM programming and ROM EPROM verification during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1 XTAL 1 XTAL 2 RESET 2 3 4 3 4 5 19
Features
- of the NMOS family plus a larger user programmable memory array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low voltage 3 3V operation The UPI-C42 is essentially a ‘‘slave’’ microcontroller or a microcontroller with a slave interface included on the chip Interface registers are included to enable the UPI device to function as a slave peripheral control.
UPI-C42 Datasheet
