28F256J3 Datasheet | Intel

Features - - - Performance - 110/115/120/150 ns Initial Access Speed - 125 ns Initial Access Speed (256 Mbit density only) - 25 ns Asynchronous Page mode Reads - 30 ns Asynchronous Page mode Reads (256Mbit density only) - 32-Byte Write Buffer - 6.8 µs per byte effective programming time Software - Program and Erase suspend support - Flash Data Integrator (FDI), mon Flash Interface (CFI) patible Security - 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User Programmable OTP Cells - Absolute Protection with VPEN = GND - Individual Block Locking - Block Erase/Program Lockout during Power Transitions - - - Architecture - Multi-Level Cell Technology: High Density at Low Cost - High-Density Symmetrical 128-Kbyte Blocks - 256 Mbit (256 Blocks) (0.18µm only) - 128 Mbit (128 Blocks) - 64 Mbit (64 Blocks) - 32 Mbit (32 Blocks) Quality and Reliability - Operating Temperature: -40 °C to +85 °C - 100K Minimum Erase Cycles per Block - 0.18 µm ETOX™ VII Process (J3C) - 0.25 µm ETOX™ VI Process (J3A) Packaging and Voltage - 56-Lead TSOP Package - 64-Ball Intel® Easy BGA Package - Lead-free packages available - 48-Ball Intel® VF BGA Package (32 and 64 Mbit) (x16 only) - VCC = 2.7 V to 3.6 V - VCCQ = 2.7 V to 3.6 V Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel Strata Flash® Memory (J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bitper-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 ponents...