3 0 MEMORY MAPS 3 1 Extended Status Registers Memory Map 4 0 BUS OPERATIONS COMMANDS AND STATUS REGISTER DEFINITIONS 4 1 Bus Operations for Word-Wide Mode (BYTE e VIH) 4 2 Bus Operations for Byte-Wide Mode (BYTE e VIL) 4 3 VE28F008 or M28F008 Compatible Mode Command Bus Definitions 4 4 VS MS28F016S
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VS28F016SV MS28F016SV 16-Mbit (1-Mbit x 16 2-Mbit x 8) FlashFile TM MEMORY
Y
VS28F016SV b 40 C to a 125 C SE2 Grade MS28F016SV b 55 C to a 125 C QML Certified SE1 Grade SmartVoltage Technology User-Selectable 3 3V or 5V VCC User-Selectable 5V or 12V VPP Three Voltage Speed Options 80 ns Access Time 5 0V g 5% 85 ns Access Time 5 0V g 10% 120 ns Access Time 3 3V g 10% 1 Million Erase Cycles per Block Typical 14 3 MB sec Burst Write Transfer Rate
Y Y Y
Configurable x8 or x16 Operation 56-Lead SSOP Plastic Package Backwards-Compatible with VE28F008 M28F008 and 28F016SA Command Set Revolutionary Architecture Multiple Command Execution Write During Erase Command Super-Set of the Intel VE28F008 M28F008 Page Buffer Write Multiple Power Savings Modes Two 256-Byte Page Buffers State-of-the-Art 0
MS28F016SV Datasheet
