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STEL2060C Datasheet PDF

Intel STEL2060C

The STEL-2060C is a specialized product designed to perform this specific communications related function. This enables accurate decoding of the information despite a high symbol error rate resulting from an impaired communications link. The STEL-2060C contains a K = 7 Viterbi Decoder.
Part No. STEL2060C
Datasheet STEL2060C Download
Manufacturer
Intel
Description 45Mbps Viterbi Decoder
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STEL2060C datasheet page 1 preview

FEATURES

s 45 Mbps Operating Rate s Constraint Length K = 7 G1 = 1718 G2 = 1338 FUNCTIONAL

DESCRIPTION

Convolutional encoding and Viterbi decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. At the encoder a stream of symbols is created which introduces a high degree of redundancy. The STEL-2060C contains a K = 7 Viterbi Decoder. The data inputs can be in offset binary or offset signed-magnitude formats, with 3-bit soft decision. Auto node sync is provided for applications where symbol uncertainty can occur. Rate 2 /3, 3/4, 4/5, 5/6, 6/7 and 7/8 punctured signals can be decoded, as well as non-punctured, Rate 1/2, signals. The polynomials and puncturing patterns used are industry standards. Depuncturing logic is incorporated into the decoder to provide automatic depuncturing of received data at rates 2/3, 3/4 and 7/8 when the puncturing patterns supported by the device are used. A BER monitor is also provided in the device, along with a circuit for computing the mean value of the BER over an extended period.
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