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TP80C251SA - (TP8xC251Sx) HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Download the TP80C251SA datasheet PDF. This datasheet also covers the TP80C251SQ variant, as both devices belong to the same (tp8xc251sx) high-performance chmos microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

at any time, without notice.

Third-party brands and names are the property of their respective owners.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O.

Box 7641 Mt.

Key Features

  • can be selected by new user-programmable configurations.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TP80C251SQ_Intel.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TP80C251SA
Manufacturer Intel
File Size 381.68 KB
Description (TP8xC251Sx) HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Datasheet download datasheet TP80C251SA Datasheet

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Other Datasheets by Intel

Part Number Description
TP80C251SB (TP8xC251Sx) HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TP80C251SP (TP8xC251Sx) HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TP80C251SQ (TP8xC251Sx) HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TP80C31BH (TP8xCx1BH) CMOS Single-Chip 8-Bit Microcontroller
TP80C51BH (TP8xCx1BH) CMOS Single-Chip 8-Bit Microcontroller

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PRELIMINARY 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express s Real-time and Programmed Wait State Bus Operation s Binary-code Compatible with MCS® 51 s Pin Compatible with 44-pin PLCC and 40pin PDIP MCS 51 Sockets s Register-based MCS® 251 Architecture — 40-byte Register File — Registers Accessible as Bytes, Words, or Double Words s Enriched MCS 51 Instruction Set — 16-bit and 32-bit Arithmetic and Logic Instructions — Compare and Conditional Jump Instructions — Expanded Set of Move Instructions s Linear Addressing s 256-Kbyte Expanded External Code/Data Memory Space s ROM/OTPROM/EPROM Options: 16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or without ROM/OTPROM/EPROM s 16-bit Internal Code Fetch s 64-Kbyte Extended Stack Space s On-chip Data RAM Options: 1-Kbyte (SA/SB)