AUIRS21271S Overview
Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is patible with standard CMOS or LSTTL outputs, down to 3.3 V. The protection circuitry detects over-current in the driven power transistor and terminates the gate drive voltage.
AUIRS21271S Key Features
- Floating channel designed for bootstrap operation
- Fully operational to +600 V
- Tolerant to negative transient voltage
- dV/dt immune VOFFSET
- Application-specific gate drive range
- Undervoltage lockout
- Desaturation Over Current Protection
- 3.3 V, 5 V, and 15 V input logic patible
- FAULT lead indicates shutdown has occurred
- Output in phase with input (AUIRS2127/AUIRS21271)