5962-8688001XA Overview
Features ARlNC Specification 429 patible The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC Data Rates of 100 Kilobits or 12.5 Kilobits Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with Separate Receiver and Transmitter Section the HS-3182, a monolithic Dl bipolar differential line driver...
5962-8688001XA Key Features
- ARlNC Specification 429 patible
- Separate Receiver and Transmitter Section the HS-3182, a monolithic Dl bipolar differential line driver
- Serial to Parallel Receiver Data Conversion Figure 1. The two receivers operate at a frequency that is ten
- Parallel to Serial Transmitter Data Conversion (10) times the receiver data rate, which can be the same or different fro
- Word Lengths of 25 or 32 Bits receivers operate at the same frequency, they are
- Parity Status of Received Data functionally independent and each receives serial data asynchronously. The transmitter se
- Generate Parity of Transmitter Data interface circuit consists mainly of a First-In First-Out (FIFO)
- Automatic Word Gap Timer memory and timing circuit. The FIFO memory is used to hold up to eight (8) ARINC data words for
- Single 5V Supply The timing circuit is used to correctly separate each ARINC word as required by ARINC Specification 429.
- Low Power Dissipation ARINC Specification 429 specifies a 32-bit word, including