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CD40193BMS - CMOS Presettable Up/Down Counters

General Description

CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.

Key Features

  • CD40192BMS - BCD Type.
  • CD40193BMS - Binary Type.
  • High Voltage Type (20V Rating).
  • Individual Clock Lines for Counting Up or Counting Down.
  • Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading.
  • Asynchronous Reset and Preset Capability.
  • Medium Speed Operation - fCL = 8MHz (typ. ) at 10V.
  • 5V, 10V and 15V Parametric Ratings.
  • Standardize Symmetrical Output Characteristics.
  • 100% Tested for Quie.

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📁 Similar Datasheet

Part Number Description Manufacturer
CD40193BM 4-Bit Up/Down Binary Counter National Semiconductor
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CD40193B CMOS PRESETTABLE UP/DOWN COUNTERS Texas Instruments
CD40193BC Synchronous 4-Bit Up/Down Decade Counter National Semiconductor
CD40193BE CMOS PRESETTABLE UP/DOWN COUNTERS Texas Instruments

Other Datasheets by Intersil (now Renesas)

Part Number Description
CD40192BMS CMOS Presettable Up/Down Counters
CD40194BMS CMOS 4-Bit Bidirectional Universal Shift Register
CD4019BMS CMOS Quad AND/OR Select Gate
CD40100BMS CMOS 32-Stage Static Left/Right Shift Register
CD40102BMS CMOS 8-Stage Presettable Synchronous Down Counters

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD40192BMS CD40193BMS December 1992 CMOS Presettable Up/Down Counters (Dual Clock With Reset) Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY and BORROW outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock.