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CD4068BMS - CMOS 8 Input NAND/AND Gate

General Description

of ‘B’ Series CMOS Devices” K=A B C D E F G H 1 A 2 B 3 C 4 D 5 NC 6 VSS 7 14 VDD 13 J = A B C D E F G H 12 H 11 G 10 F 9 E 8 NC NC = NO CONNECTION Functional Diagram A B C D 2 3 4 5 1 13 E F G H 9 10 11 12 J=A B C

Key Features

  • High Voltage Type (20V Rating).
  • Medium Speed Operation - TPHL, TPLH = 75ns (Typ. ) at VDD = 10V.
  • Buffered Inputs and Outputs.
  • 5V, 10V and 15V Parametric Ratings.
  • Standardized Symmetrical Output Characteristics.
  • 100% Tested for Quiescent Current at 20V.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VD.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4068BMS December 1992 CMOS 8 Input NAND/AND Gate Pinout CD4068BMS TOP VIEW Features • High Voltage Type (20V Rating) • Medium Speed Operation - TPHL, TPLH = 75ns (Typ.) at VDD = 10V • Buffered Inputs and Outputs • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No.