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CD4068BMS Datasheet CMOS 8 Input Nand/and Gate

Manufacturer: Intersil (now Renesas)

Overview: CD4068BMS December 1992 CMOS 8 Input NAND/AND Gate Pinout CD4068BMS TOP.

General Description

of ‘B’ Series CMOS Devices” K=A·B·C·D·E·F·G·H 1 A 2 B 3 C 4 D 5 NC 6 VSS 7 14 VDD 13 J = A · B · C · D · E · F · G · H 12 H 11 G 10 F 9 E 8 NC NC = NO CONNECTION Functional Diagram A B C D 2 3 4 5 1 13 E F G H 9 10 11 12 J=A·B·C·D·E·F·G·H K=A·B·C·D·E·F·G·H VDD = 14 VSS = 7 6, 8 = NO CONNECTION K J Description CD4068BMS NAND/AND gate provides the system designer with direct implementation of the positive logic 8 Input NAND and AND functions and supplements the existing family of CMOS gates.

The CD4068BMS is supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4H H1B H3W Logic Diagram A 2 B 3 C 4 D 5 13 J E 9 1 K F 10 G 11 H 12 FIGURE 1.

LOGIC DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge;

Key Features

  • High Voltage Type (20V Rating).
  • Medium Speed Operation - TPHL, TPLH = 75ns (Typ. ) at VDD = 10V.
  • Buffered Inputs and Outputs.
  • 5V, 10V and 15V Parametric Ratings.
  • Standardized Symmetrical Output Characteristics.
  • 100% Tested for Quiescent Current at 20V.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VD.

CD4068BMS Distributor