Datasheet Summary
CD4514BMS CD4515BMS
December 1992
CMOS 4-Bit Latch/4-to-16 Line Decoders
Pinout
CD4514BMS, CD4515BMS TOP VIEW
STROBE 1 DATA 1 2 DATA 2 3 S7 4 S6 5 S5 6 S4 7 S3 8 S2 9 S1 10 S0 11 VSS 12 24 VDD 23 INHIBIT 22 DATA 4 21 DATA 3 20 S10 19 S11 18 S8 17 S9 16 S14 15 S15 14 S12 13 S13
Features
- High-Voltage Types (20-Volt Rating)
- CD4514BMS Output “High” on Select
- CD4515BMS Output “Low” on Select
- Strobed Input Latch
- Inhibit Control
- 100% Tested for Quiescent Current at 20V
- Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC
- Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
- 5V, 10V, and...
