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CDP1020 - SMBus/I2C ACPI Dual Device Bay Controller

Datasheet Summary

Description

PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME RESET TEST 1394PR0 USBPR0 REMREQ0 SECURE0 1394PR1 USBPR1 REMREQ1 SECURE1 SDA SCK ALRT VGATE PWREN0 PWREN1 SFTLOCK0 SFTLOCK1 LEDG0 LEDA0 LEDG1 LEDA1 VLED VDD VSS CLK AD0 AD1 IN/OUT IN IN IN IN IN IN IN IN

Features

  • of this device is the on-chip level shifters that provide slew rate controlled, direct gate drive for external N-Channel MOSFETs (Intersil HUF76113DK8 recommended) to switch the device bay VID supplies. Switching an N-Channel device as opposed to a P-Channel reduces both device cost and device count, resulting in an overall lower system cost. Configuration data for the CDP1020, including subsystem vendor ID, subsystem revision, bay size and device bay capabilities are designed to be written into.

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Datasheet preview – CDP1020

Datasheet Details

Part number CDP1020
Manufacturer Intersil Corporation
File Size 154.40 KB
Description SMBus/I2C ACPI Dual Device Bay Controller
Datasheet download datasheet CDP1020 Datasheet
Additional preview pages of the CDP1020 datasheet.

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Full PDF Text Transcription

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CDP1020 Data Sheet April 1999 File Number 4704 SMBus/I 2C ACPI Dual Device Bay Controller The CDP1020 is an ACPI compliant Device Bay Controller (DBC) that can control two device bays. The controller interfaces to the host system through the industry standard I2C or System Management Bus (SMBus) and is fully compliant with Device Bay Specification 0.90. The CDP1020 is designed to be compatible with the integrated SMBus host controller of the PiiX4/PiiX6 in Intel Architecture platforms. The CDP1020 is designed to be placed on the host motherboard, on a riser, or adjacent to the Device Bay connectors. The required clock source is generated from an internal oscillator on the CLK pin, with an external RC to set the frequency.
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