HI5905
Key Features
- Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
- Low Power at 5MSPS . . . . . . . . . . . . . . . . . . . . . .350mW
- Internal Sample and Hold
- Fully Differential Architecture
- Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
- SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . >70dB
- Low Data Latency
- Internal Voltage Reference
- TTL compatible Clock Input
- CMOS compatible Digital Data Outputs
