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IP80C86-2 - CMOS 16-Bit Microprocessor

General Description

The Intersil 80C86 high performance 16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV).

Key Features

  • Compatible with NMOS 8086.
  • Completely Static CMOS Design - DC.
  • . . . . 5MHz (80C86) - DC.
  • . . .8MHz (80C86-2).
  • Low Power Operation - lCCSB.
  • . . . .500µA Max - ICCOP.
  • 10mA/MHz Typ.
  • 1MByte of Direct Memory Addressing Capability.
  • 24 Operand Addressing Modes.
  • Bit, Byte, Wo.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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80C86 March 1997 CMOS 16-Bit Microprocessor Description The Intersil 80C86 high performance 16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, minimum for small systems and maximum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Full TTL compatibility (with the exception of CLOCK) and industry standard operation allow use of existing NMOS 8086 hardware and software designs. Features • Compatible with NMOS 8086 • Completely Static CMOS Design - DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86) - DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2) • Low Power Operation - lCCSB . . . . . . . . . . . . . . . . .