Intersil ACS573MS
ACS573MS is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable (LE) is High. When the latch goes low the data is latched.| Part No. | ACS573MS |
|---|---|
| Datasheet | ACS573MS Download |
| Manufacturer |  Intersil |
| Description | Radiation Hardened Octal Three-State Transparent Latch |
| Buy | Stock & Price |
FEATURES
● Devices QML Qualified in Accordance with MIL-PRF-38535● Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96724 and Intersil’s QM Plan
● 1.25 Micron Radiation Hardened SOS CMOS
● Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
● Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)
● SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
● Dose Rate Upset . . . . . . . . . . . . . . . . >10
● Dose Rate Survivability . . . . . . . . . . . >10
● Latch-Up Free Under Any Conditions
● Military Temperature Range . . . . . . . . . . . . . . . . . . -55 oC 11 12 RAD (Si)/s, 20ns Pulse RAD (Si)/s, 20ns Pulse to +125oC D6 D7
● Significant Power Reduction Compared to ALSTTL Logic
● DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
● Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min
● Input Current ≤ 1µA at VOL, VOH
● Fast Propagation Delay . . . . . . . . . . . . . . . .
