Intersil CD4019BMS
The CD4019BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H3X 8 VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.| Part No. | CD4019BMS |
|---|---|
| Datasheet | CD4019BMS Download |
| Manufacturer |  Intersil |
| Description | CMOS Quad AND/OR Select Gate |
| Buy | Stock & Price |
FEATURES
● High Voltage Type (20V Rating)● Medium Speed Operation tPHL = tPLH = 60ns (typ.) at CL = 50pF, VDD = 10V
● Standardized Symmetrical Output Characteristics
● 100% Tested for Quiescent Current at 20V
● 5V, 10V and 15V Parametric Ratings
● Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for
DESCRIPTION
of ‘B’ Series CMOS Devices”● Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25 oC
● Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Functional Diagram Ka Kb VDD 16 9 15 14
APPLICATIONS
● And/Or Select Gating● Shift-Right/Shift-Left Registers
● True/Complement Selection
● AND/OR/Exclusive-OR Selection B4 A3 B3 A2 B2 A1 B1 1 2 3 4 5 6 7 A4 13 12 11 D4 = (A4 Ka) + (B4 Kb) 10 D4 D3 D2 D1
DESCRIPTION
CD4019BMS types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb.
