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CDP68HC68P1 Datasheet PDF

Intersil CDP68HC68P1

The CDP68HC68P1 is a serially addressed 8-bit Input/Output port that allows byte or individual bit control. It consists of three registers, an output buffer and control logic. The I/O port data flow is controlled by the Data Direction Register and data is stored in the Data Register that outputs or senses the logic levels at the buffered I/O pins.
Part No. CDP68HC68P1
Datasheet CDP68HC68P1 Download
Manufacturer
Intersil
Description CMOS Serial 8-Bit Input/Output Port
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CDP68HC68P1 datasheet page 1 preview

FEATURES

● Fully Static Operation
● Operating Voltage Range 3-6V
● Compatible with Intersil/Motorola SPI Bus
● 2 External Address Pins Tied to VDD or VSS to Allow Up to 4 Devices to Share the Same Chip Enable
● Versatile Bit-Set and Bit-Clear Capability
● Accepts Either SCK Clock Polarity - SCK Voltage Level is Latched When Chip Enable Goes Active
● All Inputs are Schmitt-Trigger
● 8-Bit I/O Port - Each Bit can be Individually Programmed as an Input or Output Via an 8-Bit Data Direction Register
● Programmable On Board Comparator PKG. NO. Ordering Information PART NUMBER CDP68HC68P1E CDP68HC68P1M TEMP. RANGE (oC) -55 to 85 -55 to 85 PACKAGE 16 Ld PDIP 16 Ld SOIC
● Simultaneous Transfer of Compare Information to CPU During Read or Write - Separate Access Not Required E16.3 M16.15 Pinout CDP68HC68P1 (PDIP, SOIC) TOP VIEW ID0 1 ID1 2 MISO 3 MOSI 4 SCK 5 CE 6 DO 7 VSS 8 16 VDD 15 D1 14 D2 13 D3 12 D4 11 D5 10 D6 9 D7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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