HCS161MS Datasheet | Intersil

Radiation Hardened Synchronous Counter Features - 3 Micron Radiation Hardened SOS CMOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) - Dose Rate Survivability: >1 x 1012 RAD (Si)/s - Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse - Cosmic Ray Upset Immunity 2 x 10-9 Error/Bit Day (Typ) - Latch-Up Free Under Any Conditions - Military Temperature Range: -55o C to +125o C - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min - Input Current Levels Ii  5A at VOL, VOH Description The Intersil HCS161MS is a Radiation Hardened 4-Input Binary; synchronous counter featuring asynchronous reset and look-ahead carry logic. The HCS161 has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (p0 - p3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCS161MS has two count output, IC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count. The HCS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS161MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). FN2469 Rev 2.00 September 1995 Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16 TOP VIEW MR 1 CP 2 P0 3 P1 4 P2 5 P3 6 PE 7 GND 8 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPEN MR CP P0 P1 P2 P3 PE...