Intersil HCS190MS
HCS190MS is an asynchronously presettable BCD Decade synchronous counter. The counter is incremented or decremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the Terminal Count output (TC), which is low during counting, goes high and remains high for one clock cycle.| Part No. | HCS190MS |
|---|---|
| Datasheet | HCS190MS Download |
| Manufacturer |  Intersil |
| Description | Radiation Hardened Synchronous 4-Bit Up/Down Counter |
| Buy | Stock & Price |
FEATURES
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● 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min Input Current Levels Ii ≤ 5µA at VOL, VOH
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DESCRIPTION
The Intersil Presetting the counter to the number on the preset data inputs (P0 - P3) is accomplished by a low on the parallel load input (PL). Counting occurs when (PL) is high, Count Enable (CE) is low and the Up/Down (U/D) input is either low for up-counting or high for down-counting. This output can be used for lookahead carry in high speed cascading. The TC output also initiates the Ripple Clock output (RC) which, normally high, goes low and remains low for the low-level portion of the clock pulse.
