Intersil HCTS109MS
HCTS109MS is a Radiation Hardened Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition of the clock (CP1 or CP2). The HCTS109MS utilizes advanced CMOS/SOS technology to achieve high-speed operation.| Part No. | HCTS109MS |
|---|---|
| Datasheet | HCTS109MS Download |
| Manufacturer |  Intersil |
| Description | Radiation Hardened Dual JK Flip Flop |
| Buy | Stock & Price |
FEATURES
● 3 Micron Radiation Hardened SOS CMOS● Total Dose 200K RAD (Si)
● SEP Effective LET No Upsets: >100 MEV-cm2/mg
● Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ)
● Dose Rate Survivability: >1 x 1012 RAD (Si)/s
● Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
● Latch-Up Free Under Any Conditions
● Military Temperature Range: -55 oC Q1 to +125oC Q1 GND
● Significant Power Reduction Compared to LSTTL ICs
● DC Operating Voltage Range: 4.5V to 5.5V
● LSTTL Input Logic Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min
● Input Current Levels Ii ≤ 5µA at VOL, VOH 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW R1 J1 K1 CP1 S1 Q1 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC R2 J2 K2 CP2 S2 Q2 Q2
DESCRIPTION
The Intersil This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS109MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Ordering Informatio...
