Intersil HCTS112MS
HCTS112MS is a Radiation Hardened dual JK flip-flop with set and reset. The flip-flop changes states with the negative transition of the clock (CP1N or CP2N). The HCTS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation.| Part No. | HCTS112MS |
|---|---|
| Datasheet | HCTS112MS Download |
| Manufacturer |  Intersil |
| Description | Radiation Hardened Dual JK Flip-Flop |
| Buy | Stock & Price |
FEATURES
● 3 Micron Radiation Hardened SOS CMOS● Total Dose 200K RAD (Si)
● SEP Effective LET No Upsets: >100 MEV-cm2/mg
● Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ)
● Dose Rate Survivability: >1 x 1012 RAD (Si)/s
● Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
● Cosmic Ray Upset Rate 2 x 10-9 Errors/Bit Day (Typ)
● Latch-Up Free Under Any Conditions
● Military Temperature Range: -55 oC to +125oC GND 8
● Significant Power Reduction Compared to LSTTL ICs
● DC Operating Voltage Range: 4.5V to 5.5V
● LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min
● Input Current Levels Ii ≤ 5µA at VOL, VOH CP1 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16 TOP VIEW 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC R1 R2 CP2 K2 J2 S2 Q2
DESCRIPTION
The Intersil This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS112MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). K1 J1 S1 Q1...
