Intersil HCTS161AMS
The HCTS161AMS has an active-low master reset to zero, MR. The data is latched to the outputs on the positive edge of the clock input, CP. The HCTS161AMS has two count enable pins, PE and TE.| Part No. | HCTS161AMS |
|---|---|
| Datasheet | HCTS161AMS Download |
| Manufacturer |  Intersil |
| Description | Radiation Hardened Synchronous Counter |
| Buy | Stock & Price |
FEATURES
● 3 Micron Radiation Hardened CMOS SOS● Total Dose 200K RAD (Si)
● Minimum LET for SEU Upsets: >100 MEV-cm2/mg
● Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)
● Dose Rate Survivability: >1 x 1012 RAD (Si)/s
● Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
● Latch-Up Free Under Any Conditions
● Military Temperature Range: -55oC to +125oC
● Significant Power Reduction Compared to LSTTL ICs
● DC Operating Voltage Range: 4.5V to 5.5V
● Input Logic Levels -VIL = 0.8V Max -VIH = VCC/2V Min
● Input Current Levels Ii ≤ 5µA at VOL, VOH
DESCRIPTION
The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (P0 - P3) to load the counter. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count.
