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HCTS299MS Datasheet PDF

Intersil HCTS299MS

HCTS299MS is a Radiation Hardened 8-bit shift/ storage register with three-state bus interface capability. The register has four synchronous operating modes controlled by the two select inputs (S0, S1). The mode select, the serial data (DS0, DS7) and the parallel data (IO0 - IO7) respond only to the low to high transition of the clock (CP) pulse.
Part No. HCTS299MS
Datasheet HCTS299MS Download
Manufacturer
Intersil
Description Radiation Hardened 8-Bit Universal Shift Register
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HCTS299MS datasheet page 1 preview

FEATURES

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● 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Fanout (Over Temperature Range) -Bus Driver Outputs: 15 LSTTL Loads Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V LSTTL Input Compatibility -VIL = 0.8V Max -VIH = VCC/2 Min Input Current Levels Ii ≤ 5µA at VOL, VOH GND 10
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DESCRIPTION

The Intersil S0, S1 and the data inputs must be one set up time period prior to the clocks positive transition. The master reset (MR) is an asynchronous active low input. The HCTS299MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family with TTL input compatibility.
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