DESCRIPTION
The data and clock inputs and data outputs are DC coupled. At the data input port, the iT4005D tolerates a wide range of operating conditions, and the internal 50-ohm resistors avoid the need for external terminations for impedance matching. The iT4005D uses SCFL I/O levels and allows either single-ended or differential data input and output. For the clock, a single-ended, DC-coupled input with an internal 50-ohm resistor followed by a DC block is provided. An amplitude of 700 mV peak-to-peak for the clock is recommended, although depending on the operating frequency, a lower amplitude may be usable. An on-chip output buffer provides an excellent eye diagram at a 12.5 GHz clock frequency. FEATURES
2-13 GHz clock frequency range 900 mVpp single ended output dynamic Output rise time (20%-80%): 25 ps Output fall time (20%-80%): 24 ps DC coupled clock input DC coupled data input 50 ohm matched DC-coupled data output Differential or single-ended inputs Low powe...
