DESCRIPTION
APPLICATIONS
include XOR logic up to 12.5 Gb/s, edge detection and Manchester encoding up to 10.709 Gb/s, and X2 clock multiplication with inputs up to 6.25 GHz. Data inputs and output are DC coupled, and internal 50-ohm resistors at the input eliminate the need for external impedance matching terminations. Inputs can be either single-ended or differential, and a highperformance output buffer ensure superior eye diagram performance. FEATURES
Data rate range: DC to 12.5 Gb/s Typical single-ended output : 800 mVpp Input sensitivity: >300 mV (single-ended) Jitter RMS < 1.8 ps Output rise time (20% to 80%): < 22 ps Output fall time (20% to 80%): < 19 ps 50-ohm matched DC-coupled inputs and outputs Differential or single-ended I/O Power consumption: 750 mW Device Diagram This is an Advanced data sheet. See “Product Status Definitions” on Web site or catalog for product development status. August 8, 2005 Doc. 1488 Rev 0 1 iTerra Communications 2400 Geng Road, Ste.
