DESCRIPTION
Complex digital applications that can benefit from the iT4032D include clock data recovery, edge detectors, NRZ/RZ converters, MUX/DEMUX, and data restoration It is based on an ECL topology in order to guarantee high-speed operation. shift capability. The delay control can be either differential (using both VCp and VCm) or single-ended (VCp is the active control pad while VCm is shorted to VCref). The nominal control voltage range for the delay is from -2.2 V to -3.0 V, whether the control is single-ended or differential. The flipping control can be either differential (using both VFp and VFn), or single-ended (VFp is the active control pad while VFm is shorted to VCref). The nominal control voltage for the flipping is -2.2 V or -3.0 V whether the control is single-ended or differential. The device is capable of delaying NRZ streams with a data rate up to 12.5 Gb/s or a clock signal with frequency up to 10.7 GHz. The inputs and the outputs are DC coupled. At the input side the internal 50-ohm resistors avoid the need for external impedance matching terminations.
