JMB368 Description
PCI Express to PATA Host Controller Document 1 JMB368 Data Sheet 2 JMB368 Design Specification 3 JMB368 Hardware Design Guide 4 JMB368 Hardware Schematic Contact Information Department Sales Tech. Support Email sales@jmicron. Copyright © 2006 JMicron Technology Corp.
JMB368 Key Features
- pliant with Bus Master Programming interface for IDE ATA Controllers Revision 1.0
- pliant with PCI Express Base Spec. Revision 1.0a
- pliant with PCI IDE Controller Spec. Revision 1.0
- pliant with SFF-8038i Bus Master Programming Interface Revision 1.0 Overall
- Integrated 1-Lane PCI Express PHY
- Output swing control and Automatic impedance calibration for PCI Express PHY
- Fabricated 0.18um/3.3V UMC CMOS Standard Logic Process with 2.0V and 3.3V
- Available in 48-pin LQFP package
- Co-layout with JMB361 and JMB363 PCI Express
- Supports 1-Lane 2.5Gbps PCI Express bus