Datasheet4U Logo Datasheet4U.com

KK16C554TQ - QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT

This page provides the datasheet information for the KK16C554TQ, a member of the KK16C554PL QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT family.

Datasheet Summary

Description

KK16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter).

Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead.

Features

  • z z z z z z z z In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrupts to CPU. Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data. Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial data. Independently controlled transmit, receive, line status and data interrupts. Programmable Baud Rate Generators which allow division of.

📥 Download Datasheet

Datasheet preview – KK16C554TQ

Datasheet Details

Part number KK16C554TQ
Manufacturer KODENSHI KOREA
File Size 869.84 KB
Description QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT
Datasheet download datasheet KK16C554TQ Datasheet
Additional preview pages of the KK16C554TQ datasheet.

📁 Similar Datasheet

Other Datasheets by KODENSHI KOREA
  • KK16C554PL - QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT
  • KK100-6 - Sensitive Gate Silicon Controlled Rectifiers
  • KK1207 - specifically designed
  • KK1232 - POWER SUPPLY CONTROL
  • KK135Z - Integrated circuit of temperature sensor
  • KK145567 - PCM CODEC - FILTER
  • KK1458 - Dual Operational Amplifiers
  • KK1488 - Quadruple Line Drivers

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com KK16C554PL/KK16C554TQ QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT 1. General Description KK16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter). Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes. Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation.
Published: |