KK74HC74A
KK74HC74A is Dual D Flip-Flop manufactured by Kodenshi AUK Group.
TECHNICAL DATA
Dual D Flip-Flop with Set and Reset
The KK74HC74A is identical in pinout to the LS/ALS74. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LS/ALSTTL outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous.
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION KK74HC74AN Plastic KK74HC74AD SOIC TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Set L H L PIN 14 =VCC PIN 7 = GND H H H H Reset H L L H H H H L H Clock X X X Data X X X H L X X Outputs Q H L H
- Q L H H- L H
No Change No Change
H H X No Change
- Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don’t care
..net
MAXIMUM RATINGS-
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
- Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package-
- Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
- -
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260
Unit V V V m A m A m A m W °C °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions.
- - Derating
- Plastic DIP:
- 10 m W/°C...
