GENERAL DESCRIPTION
In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes. The CPU can read the complete status of the UART at any time during the functional operation. The Status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing, and break interrupt. KK16C554 includes a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to 216-1, and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this clock to drive the receiver logic. KK16C554 has complete MODEM-control capability and an interrupt system that can be programmed to the user’s requirements, minimizing the computing required to handle the communication links. 2. FEATURES
z z z z z z z z In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrupts to CPU.
Kodenshi AUK Group
