KK74AC109 Datasheet | Kodenshi AUK Group

TECHNICAL DATA .. Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are patible with standard CMOS outputs, with pullup resistors, they are patible with LS/ALS outputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop. - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 2.0 to 6.0 V - Low Input Current: 1.0 µA; 0.1 µA @ 25°C - High Noise Immunity Characteristic of CMOS Devices - Outputs Source/Sink 24 m A ORDERING INFORMATION K KK74AC109N Plastic KK74AC109D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H H PIN 16=VCC PIN 8 = GND Reset H L L H H H H Clock X X X J X X X L H L H K X X X L L H H Outputs Q H L H - Q L H H- H Toggle No Change H L H H L X X No Change X = Don’t care - Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. .. MAXIMUM RATINGS- Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL - Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V m A m A m A m W °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions. +Derating - Plastic...