KK74ACT74 Datasheet | Kodenshi AUK Group

TECHNICAL DATA .. Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The KK74ACT74 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. - TTL/NMOS patible Input Levels - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 4.5 to 5.5 V - Low Input Current: 1.0 µA; 0.1 µA @ 25°C - Outputs Source/Sink 24 m A ORDERING INFORMATION KK74ACT74N Plastic KK74ACT74D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H H PIN 14 =VCC PIN 7 = GND Reset H L L H H H H L H Clock X X X Data X X X H L X X Outputs Q H L H - Q L H H- L H No Change No Change H H X No Change - Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don’t care .. MAXIMUM RATINGS- Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL - Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V m A m A m A m W °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions....