ML610Q384 Datasheet | LAPIS Semiconductor

DESCRIPTION Equipped with a 8-bit CPU n X-U8/100, the ML610Q380/383/384/385 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as 12-bit A/D converter, timer, PWM, synchronous serial port, UART, I２C bus interface (master), Battery level detect circuit, LCD driver, voice output function and speaker amplifier. The n X-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board. FEATURES - CPU - 8-bit RISC CPU (CPU name: n X-U8/100) - Instruction system:16-bit instructions - Instruction set:Transfer, arithmetic operations, parison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - On-Chip debug function - Minimum instruction execution time Approx 30.5 μs (at 32.768k Hz system clock) Approx 0.122 μs (at 8.192MHz system clock)＠DVDD = 2.2 to 5.5V - Internal memory - Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is included) - Has 2-Kbyte RAM (2048 × 8 bits) built in. - Has maximum of 16-Mbit P2ROM (only ML610Q383/384/385) P2ROM capacity: ML610Q383 (4M bit), ML610Q384 (8M bit), and ML610Q385 (16M bit) - Interrupt controller - 2 non-maskable interrupt sources (Internal source: 1, External source: 1) - 24 maskable interrupt sources (Internal source: 20, External source: 4) - Time base counter - Low-speed time base counter × 1 channel - High-speed time base counter × 1 channel - Watchdog timer - Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second - Free running - Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) - Timers - 8 bits × 6ch (16-bit configuration...