Datasheet4U Logo Datasheet4U.com

ML610Q436 - 8-bit Microcontroller

This page provides the datasheet information for the ML610Q436, a member of the ML610Q435 8-bit Microcontroller family.

Description

This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as real-time clock, synchronous serial port, UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit successive approximation type A/D

Features

  • CPU.
  • 8-bit RISC CPU (CPU name: nX-U8/100).
  • Inst.

📥 Download Datasheet

Datasheet preview – ML610Q436

Datasheet Details

Part number ML610Q436
Manufacturer LAPIS Semiconductor
File Size 773.13 KB
Description 8-bit Microcontroller
Datasheet download datasheet ML610Q436 Datasheet
Additional preview pages of the ML610Q436 datasheet.

📁 Similar Datasheet

  • ML610Q418 - 8-bit Microcontroller (LAPIS)
  • ML610Q418C - 8-bit Microcontroller (LAPIS)
  • ML610Q426 - 8-bit Microcontroller (LAPIS)
  • ML610Q327 - 8-bit Microcontroller (LAPIS)
  • ML610Q328 - 8-bit Microcontroller (LAPIS)
  • ML610Q329 - 8-bit Microcontroller (LAPIS)
  • ML610Q772 - 8-bit Microcontroller (LAPIS)
  • ML6101 - Voltage Monitor (Minilogic Device Corporation)
  • ML6101A - (ML6101A - ML6701A) AIGaAs Laser Diodes emitting light beams around 780nm wavelength (Mitsubishi Electric)
  • ML610401 - 8-bit Microcontroller (LAPIS)
Other Datasheets by LAPIS Semiconductor

Full PDF Text Transcription

Click to expand full text
ML610Q435/ML610Q436 8-bit Microcontroller with a Built-in LCD driver FEDL610Q435-03 Issue Date: Apr.8, 2015 GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as real-time clock, synchronous serial port, UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing.
Published: |