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ML620Q155A - 16-bit micro controller

Download the ML620Q155A datasheet PDF. This datasheet also covers the ML620Q151A variant, as both devices belong to the same 16-bit micro controller family and are provided as variant models within a single manufacturer datasheet.

General Description

This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter, timer, PWM, synchronous serial port, UART, I2C bus interface (master), Low level detect circuit, are incorporated around 16-bit CPU nX-U16/100.

Key Features

  • CPU.
  • 16-bit RISC CPU (CPU name: nX-U16/100).
  • Instruction system:16-bit instructions.
  • Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on.
  • On-Chip debug function.
  • Minimum instruction execution time Approx 30.5 µs (at 32.768kHz system clock) Approx 0.122 µs (at 8.192M.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ML620Q151A-LAPISSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ML620Q155A
Manufacturer LAPIS Semiconductor
File Size 744.71 KB
Description 16-bit micro controller
Datasheet download datasheet ML620Q155A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
FEDL620Q150A-01 Issue Date: May 7, 2015 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A 16-bit micro controller GENERAL DESCRIPTION This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter, timer, PWM, synchronous serial port, UART, I2C bus interface (master), Low level detect circuit, are incorporated around 16-bit CPU nX-U16/100. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. and, this LSI has a data flash-memory fill area by a software which can be written in. In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board.