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ML620Q504H - Ultra Low Power 16-bit Microcontroller

Download the ML620Q504H datasheet PDF. This datasheet also covers the ML620Q503H variant, as both devices belong to the same ultra low power 16-bit microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D converter, and successive approximation type A/D converter are incorp

Key Features

  • CPU.
  • 16-bit RISC CPU (CPU name.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ML620Q503H-LAPIS.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ML620Q504H
Manufacturer LAPIS
File Size 901.32 KB
Description Ultra Low Power 16-bit Microcontroller
Datasheet download datasheet ML620Q504H Datasheet

📁 Similar Datasheet

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Other Datasheets by LAPIS

Part Number Description
ML620Q503H Ultra Low Power 16-bit Microcontroller
ML620Q131 16-bit micro controller
ML620Q131B 16-bit micro controller
ML620Q132 16-bit micro controller
ML620Q132B 16-bit micro controller

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ML620Q503H/Q504H Ultra Low Power 16-bit Microcontroller FEDL620Q504H-01 Issue Date: Aug. 31, 2015 GENERAL DESCRIPTION This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D converter, and successive approximation type A/D converter are incorporated around 16-bit CPU nX-U16/100. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel processing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) is most suitable for battery-driven applications.