ML62Q1600 Datasheet | LAPIS

DESCRIPTION ML62Q1600 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU n X-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC operator, DMA controller, clock generator, simplified RTC, timer, UART, synchronous serial port, I2C bus interface unit, buzzer, Voltage Level Supervisor(VSL), successive approximation type A/D converter, D/A converter , analog parator, LCD driver, safety function and etc. The CPU n X-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipeline architecture parallel processing. The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming) function supports the Flash programming in production line. The ML62Q1600 Group has five packages (48pin - 64pin) and five kinds of memory sizes(32Kbyte - 64Kbyte). Program memory 64Kbyte 48Kbyte 32Kbyte Table 1 ML62Q1600 Group Product List Data memory (RAM) Data Flash 48pin TQFP48 52pin TQFP52 4Kbyte 4Kbyte 4Kbyte 2Kbyte 2Kbyte 2Kbyte ML62Q1602 ML62Q1601 ML62Q1600 ML62Q1612 ML62Q1611 ML62Q1610 64pin QFP64 TQFP64 ML62Q1622 ML62Q1621 ML62Q1620 FEATURES - CPU - 16-bit RISC CPU (CPU name: n X-U16/100) - Instruction system: 16-bit length instruction ‒ Instruction set: Transfer, arithmetic operations, parison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ‒ On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000) ‒ ISP (In-System Programming) function built-in ‒ Minimum instruction execution time 30.5 μs (at 32.768 KHz system clock) 62.5ns/41.6ns (at 16 MHz/24MHz system clock) - Coprocessor for multiplication and division - Multiplication: 16bit × 16bit (operation time 4 cycles) - Division: 32bit / 16bit (operation time 8 cycles) -...