LF3324

LF3324 Key Features

• 3,110,400 x 8-bit
• 2,488,320 x 10-bit
• 2,073,600 x 12-bit Operating Modes
• Random Access with Burst Control
• Synchronous Shift Register Near-Full/Empty Flags With Programmable Thresholds Flexible Pointer Manipulation
• Write and Read Pointers may be independently jumped to arbitrary address locations
• Write or Read Pointers can be manipulated in realtime based on external 24bit address LF3324s may be Cascaded for depth
• Seamless address space is maintained with up to 8 cascaded devices Built-in ITU-R BT.656 TRS detection and Synchronizati
• Two-wire Serial Microprocessor Interface
• Parallel Microprocessor Interface Input Enable Control (Write Mask) for freezeframe