DESCRIPTION
An 8 x 8 multiplier, three decimation registers, and a 26-bit accumulator are contained in each filter cell. 8-bit unsigned or two’s complement format for data and coefficients can be independently selected. Expanded coefficients and word sizes can be processed by cascading multiple LF43881s to implement larger filter lengths without affecting the sample rate. By reducing the sample rate, a single LF43881 can process larger filter lengths by using multiple passes. The sampling rate can range from 0 to 40 MHz. Over 1000 taps may be processed without overflows due to the architecture of the device. The output sample rate can be reduced to one-half, one-third, or onefourth the input sample rate by using the three decimation registers contained in every filter cell. Matrix multiplication, N x N spatial correlations/convolutions, and other 2-D operations for image processing can also be achieved using these registers. FEATURES
u u u u 25 MHz Maximum Sampling Rate 320 MHz Multipl...
LOGIC Devices Incorporated
