LMA1009 Datasheet PDF - LOGIC Devices Incorporated 12 x 12-bit Multiplier-Accumulator Specs

LMA1009 - 12 x 12-bit Multiplier-Accumulator

Datasheet Summary

Description

Data present at the A and B input registers is latched on the rising edges of CLK A and CLK B respectively.

RND, TC, ACC, and SUB controls are latched on the rising edge of the logical OR of CLK A and CLK B.

TC specifies the input as two’s complement (TC HIGH) or unsigned magnitude (TC LOW).

Features

u 20 ns Multiply-Accumulate Time u Low Power CMOS Technology u Replaces Fairchild TDC1009/ TMC2009 u Two’s Complement or Unsigned Operands u Accumulator Performs Preload, Accumulate, and Subtract u Three-State Outputs u 68-pin PLCC, J-Lead LMA1009/2009 BLOCK.

Datasheet Details

Part number	LMA1009
Manufacturer	LOGIC Devices Incorporated
File Size	189.68 KB
Description	12 x 12-bit Multiplier-Accumulator
Datasheet	LMA1009 Datasheet
Additional preview pages of the LMA1009 datasheet.

📁 Similar Datasheet

LMA110 - .5-6 GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA110 - .5-8GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA110A - .5-6 GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA110B - .5-8GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA1117 - 1A Low Dropout Positive Adjustable (Kexin)

LMA116 - 2-10GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA183 - 2-18 GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA184 - 2-18 GHz MESFET Amplifier (Filtronic Compound Semiconductors)

LMA208C - 2-26 GHz PHEMT Amplifier (Filtronic Compound Semiconductors)

LMA208G - 2-26GHz PHEMT Amplifier (Filtronic Compound Semiconductors)

Full PDF Text Transcription

Click to expand full text

LMA 1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator LMA1009/2009 DEVICES INCORPORATED 12 x 12-bit Multiplier-Accumulator DESCRIPTION Data present at the A and B input registers is latched on the rising edges of CLK A and CLK B respectively. RND, TC, ACC, and SUB controls are latched on the rising edge of the logical OR of CLK A and CLK B. TC specifies the input as two’s complement (TC HIGH) or unsigned magnitude (TC LOW). RND, when HIGH, adds ‘1’ to the most significant bit position of the least significant half of the product. SubThe LMA1009/2009 produces the 24-bit sequent truncation of the 12 least signifiproduct of two 12-bit numbers. The cant bits produces a result correctly results of a series of multiplications may rounded to 12-bit precision.

Published: Apr 25, 2005 |