DESCRIPTION
The LMS12 implements the general form (A●B) + C. As a result, it is also useful in implementing polynomial approximations to transcendental functions. ARCHITECTURE A block diagram of the LMS12 is shown below. Its major features are discussed individually in the following paragraphs. MULTIPLIER The A11-0 and B11-0 inputs to the LMS12 are captured at the rising edge of the clock in the 12-bit A and B input registers, respectively. These registers are independently enabled by the ENA and ENB inputs. The registered input data are then applied to a 12 x 12-bit multiplier array, which produces a 24-bit result. Both the inputs and outputs of the multiplier are in two’s complement format. The multiplication result forms the input to the 24-bit product register. SUMMER The C 25-0 inputs to the LMS12 form a 26-bit two’s complement number which is captured in the C register at the rising edge of the clock. The C register is enabled by assertion of the ENC input. The summer is a 26-bit adder which operates on the C register data and the sign extended contents of the product register to produce a 26-bit sum.
LOGIC Devices Incorporated
