LPR520 Datasheet | LOGIC Devices Incorporated

DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register DESCRIPTION The LPR520 is functionally patible with the L29C520 but have 16-bit inputs and outputs. The LPR520 is implemented in low power CMOS. The LPR520 contains four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline. The Instruction pins, I1-0, control the loading of the registers. The registers may be configured as a four-stage delay line, with data loaded into R1 and shifted sequentially through R2, R3, and R4. Also, data may be loaded from the inputs into either R1 or R3 with only R2 or R4...