L74VHC1G50 Datasheet | LRC

LESHAN RADIO PANY, LTD. Noninverting Buffer / CMOS Logic Level Shifter The L74VHC1G50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is posed of three stages, including a buffer output which provides high noise immunity and stable output. The L74VHC1G50 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the L74VHC1G50 to be used to interface 5 V circuits to 3 V circuits. - High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V - Low Power Dissipation: I CC = 2 m A (Max) at T A = 25°C - TTL- patible Inputs: V IL = 0.8 V; V IH = 2.0 V - CMOS- patible Outputs: V OH > 0.8 V CC ; V OL < 0.1 V CC @Load - Power Down Protection Provided on Inputs and Outputs - Balanced Propagation Delays - Pin and Function patible with Other Standard Logic Families - Chip plexity: FETs = 104; Equivalent Gates = 26 MARKING DIAGRAMS 5 4 1 2 3 VLd SC- 70/SC- 88A/SOT- 353 DF SUFFIX Pin 1 d = Date Code 5 4 Figure 1. Pinout (Top View) 1 2 3 VLd Figure 2. Logic Symbol Pin 1 d = Date Code SOT- 23/TSOP- 5/SC- 59 DT SUFFIX PIN ASSIGNMENT 1 2 3 4 5 NC IN A GND OUT Y V CC FUNCTION TABLE Inputs A L H Output Y L H ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. .. 1/6 LESHAN RADIO PANY,...