LS7060 Datasheet | LSI Computer Systems

FEATURES : - DC to 15 MHz Count Frequency - Byte Multiplexer - DC to 1 MHz Scan Frequency - +4.75V to +5.25V Operation (VDD-VSS) - Three-State Data Outputs, Bus and TTL patible - Inputs TTL and CMOS patible - Unique Cascade Feature Allows Multiplexing of Successive Bytes of Data in Sequence in Multiple Counter Systems - Low Power Dissipation - LS7060, LS7062 (DIP); LS7060-S, LS7062-S (SOIC) See Figures 1 and 2 DESCRIPTION : The LS7060/LS7062 is a monolithic, ion implanted MOS Silicon Gate, 32 bit/dual 16 bit up counter. The IC includes latches, multiplexer, eight three-state binary data output drivers and output cascading logic. DESCRIPTION OF OPERATION: 32 (16) BIT BINARY UP COUNTER - LS7060 (LS7062) The 32(16) bit static ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 4µs (2µs) - transition count of 32(16) ones to 32(16) zeros. Guaranteed count frequency is DC to 15MHz. See Figure 9A(9B) for Block Diagram. COUNT, ALT COUNT (LS7060) Input count pulses to the 32 bit counter may be applied through either of these two inputs. The ALT COUNT input circuitry contains a Schmitt trigger network which allows proper counting with "infinitely" long clock edges. A high applied to either of these two inputs inhibits counting. COUNT A, ALT COUNT A (LS7062) Input count pulses to the first 16 bit counter may be applied through either of these two inputs. The ALT COUNT A input circuitry contains a Schmitt trigger network which allows proper counting with “infinitely” long clock edges. A high applied to either of these two inputs inhibits counting. RESET All 32 counter bits are reset to zero when RESET is brought low for a minimum of 1µs. RESET must be high for a minimum of 300ns before next valid count can be recorded. TEST COUNT (LS7060) Count pulses may be applied to the last 16 bits of the binary counter through this input, as long as Bit 16 of the counter is a low. The counter advances on the negative transition of these...