Description
General Description 1.2 Typical Application 1.3 Features Summary L64724 Signal Definitions 2.1 Channel Interface 2.2 Channel Clock Interface 2.3 Phase-Locked Loop (PLL) Interface 2.4 Control Signals Interface 2.5 AGC/Clock Control Interface 2.6 Channel Data Output Interface 2.7 Analog-to-Digital Converter (ADC) Interface 2.8 Microcontroller Interfaceea L64724 Registers 3.1 L64724 Register Overview 3.2 Reset and How it Affects Registers 3.3 Groups 0 and 1: Address Pointer Register 3.4 Group 2: System Mode and System Status Registers 3.5 Group 3: Status Registers 3.6 Group 4: Configuration Registers 3.7 Group 5: Self-Tuning Microcontroller Registers 3.8 Group 6: Reserved (Internal Use Only) 3.9 Group 7: Arbiter Control Register 3.10 Reset Effect on Register Bits 3.11 Internal Data Path Reset Effects 1-1 1-3 1-5 Chapter 2 2-3 2-4 2-4 2-5 2-6 2-6 2-7 2-8 Chapter 3 3-1 3-7 3-8 3-9 3-23 3-33 3-77 3-81 3-81 3-82 3-84.
Key Features
- D-2 D-2 D-5 D-5 Appendix E E-2 E-5 Contents v Figures 1.1 1.2 2.1 3.1 3.2 3.3 3.4 3.5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 L64724 Block Diagram Set-Top Decoder Box Block Diagram L64724 Logic Symbol Register File Structure Issue a Hard Reset Initialize APR0 and APR1 to Zero Write Locations 0 and 1 in Group 4 Read Back Group 4 L64724 Clocking: Internal PLL PLL Clock Synthesis L64724 Functional Blocks in the Decoding Pipeline CLK and Analog Inputs for Channel Data Input CLK and Digital Inputs for ADC Bypass Mode Parallel Output Interface Waveforms Descrambler Parallel Output Waveforms Descrambler Serial Output Waveforms Demodulator Module and Associated Circuitry Input Quantization Clock Recovery Loop Timing Loop Sweep Operation Carrier Recovery Loop Frequency Sweeping SNR Threshold vs. Es/No Carrier Loop Filter Parameters Eye Pattern and ADC Range AGC Loop Control Synchronization Module Viterbi Decoder Synchronization Phase Rotation for Synchronization Channel Symbol Error Rate vs. SNR for Rate = 1/2 Channel Symbol Error Rate vs. SNR for Rate = 2/3 Channel Symbol Error Rate vs. SNR for Rate = 3/4 Channel Symbol Error Rate vs. SNR for Rate = 5/6 Channel Symbol Error Rate vs. SNR for Rate = 6/7 Channel Symbol Error Rate vs. SNR for Rate = 7/8 Reed-Solomon, Deinterleaver Synchronization 1-2 1-4 2-2 3-3 3-5 3-5 3-6 3-6 4-2 4-4 4-12 4-13 4-13 4-15 4-16 4-17 5-2 5-3 5-8 5-11 5-12 5-13 5-17 5-17 5-20 5-22 6-2 6-3 6-4 6-5 6-5 6-6 6-6 6-7 6-7 6-8 Code Code Code Code Code Code vi Contents
- 11 6.12 6.13 6.14 6.15 6.16 6.17 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.9 A.1 A.2 A.3 A.4 A.5 Synchronization, Tracking, and Loss of Sync for Three Missed Sync Words Minimum and Maximum Number of States in the Acquisition Phase Minimum and Maximum Number of States in the Tracking Phase DSS Packet MPEG-2 Transport Packet L64724 Transport Packet Descrambler Synchronization Viterbi Decoder Block Diagram Puncturing and Depuncturing Block Diagram Puncture Pattern for Different Code Rates Block Diagram of Viterbi Bit Error Detection Circuit Interleaving/Deinterleaving Operation for DVB Interleaving/Deinterleaving Operation for DSS Code Word Structure FEC Data Path 122-Bit Burst Example Descrambler Block Diagram 15-Bit Shift Register Initialization Inverted Sync Words in Descrambler AC Test Load and Waveform for Standard Outputs AC Test Load and Waveforms for 3-State Outputs L64724 Synchronous AC Timing L64724 RESET Timing Diagram L64724 Bus 3-State Delay Timing L64724 Decoder Read Cycle L64724 Decoder Write Cycle 100-Pin PQFP/MQFP Pinout 100-Pin PQFP/MQFP Mechanical Drawing 100-Pin PQFP/MQFP Mechanical Drawing (Cont.) Serial Bus Architecture 7-Bit Slave Address for the L64724 Serial Bus Serial Bus Write/Read Cycle Overview General Call Structure Burst Write or Single Write to Slave (Master-Transmitter, Slave-Receiver)
