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ZSP540 - Highly Efficient Quad-MAC DSP Core
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O V E RV I E W
The ZSP540 processor core is a high-performance/power-efficient QuadMAC/Six-ALU implementation of the ZSP® G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance/power/size and memory utilization efficiency. The Z.Turbo feature provides the SOC designer with the option to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic.
C O R E F E AT U R E S
• Quad-MAC/Six-ALU DSP core • 4+1 instructions per cycle • Up to 350MHz, 8-stage pipeline design • Up to 1750 million instructions/sec • Dual 64-bit wide Load/Store data ports • Z.Turbo coprocessor extensions capable
TARGET MARKETS
• 2.
ZSP540 Datasheet
